az100lve210 ecl/pecl 1:4, 1:5 differential clock driver 1630 s. stapley dr., suite 125 ? mesa, arizona 85204 ? usa ? (480) 962-5881 ? fax (480) 890-2541 www.azmicrotek.com arizona microtek, inc. features ? operating range of 3.0v to 5.5v ? low skew ? guaranteed skew spec ? differential design ? v bb output ? 75k ? internal input pulldown resistors ? direct replacement for on semiconductor mc100lve210 & mc100e210 description the az100lve210 is a low skew 1:4, 1:5 fanout buffer designed with clock distribution in mind. the device features fully differential clock paths to minimize both device and system skew. the az100lve210 offers two selectable clock inputs allowing redundant or test cloc ks to be incorporated into the system clock trees. the az100lve210 provides a v bb output for single-ended use or a dc bias reference for ac coupling to the device. for single?ended input applications, the v bb reference should be connected to one side of the clka/clkb differential input pair. the input signal is th en fed to the other clka/clkb input. the v bb should only be used as a bias for its sink/source capability is limited. when used, the v bb pin should be bypassed to ground via a 0.01 f capacitor. both sides of the differential output must be terminated into 50 ? to ensure that the tight skew specification is met, even if only one side is used. in most applicati ons all eight differential pairs will be used and therefore terminated. in the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the same v cco ) as the pairs being used should be terminated to maintain minimum skew. failure to do this will result in small degradations of propagation delay (on the order of 10?20ps) of the outputs being used; while not being catastrophic to most designs this will result in an increase in skew. note: specifications in the ecl/pecl tables are valid when thermal equilibrium is established. package availability package part no. marking plcc 28 az100lve210fn azm100lve210 plcc 28 t&r AZ100LVE210FNR2 azm100lve210
az100lve210 march 2002 * rev - 3 www.azmicrotek.com 2 absolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic rating unit v cc pecl power supply (v ee = 0v) 0 to +8.0 vdc v i pecl input voltage (v ee = 0v) 0 to +6.0 vdc v ee ecl power supply (v cc = 0v) -8.0 to 0 vdc v i ecl input voltage (v cc = 0v) -6.0 to 0 vdc i out output current --- continuous --- surge 50 100 ma t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c 100k ecl dc characteristics (v ee = -3.0v to -5.5v, v cc = v cco = gnd) -40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit v oh output high voltage 1 -1085 -1005 -880 -1025 -955 -880 -1025 -955 -880 -1025 -955 -880 mv v ol output low voltage 1 -1830 -1695 -1555 -1810 -1705 -1620 -1810 -1705 -1620 -1810 -1705 -1620 mv v ih input high voltage -1165 -880 -1165 -880 -1165 -880 -1165 -880 mv v il input low voltage -1810 -1475 -1810 -1475 -1810 -1475 -1810 -1475 mv v bb reference voltage -1380 -1260 -1380 -1260 -1380 -1260 -1380 -1260 mv i ih input high current 150 150 150 150 a i il input low current 0.5 0.5 0.5 0.5 a i ee power supply current 55 60 55 60 55 60 65 70 ma 1. each output is terminated through a 50 ? resistor to v cc ? 2v. logic symbol qa0 qa0 qa1 qa1 qa2 qa2 qa3 qa3 qb0 qb0 qb1 qb1 qb2 qb2 qb3 qb3 clka clkb clka clkb v bb qb4 qb4 pin description pin function clka, clk a differential input pairs clkb,clk b differential input pairs qa0, q a0 - qa3, q a3 differential output pairs qb0, q b0 - qb4, q b4 differential output pairs v bb v bb output v cc , v cco positive supply v ee negative supply v ee clkb v bb clka clka clkb v cc qb4 qa1 qa1 qa0 qa0 qa2 qa2 qa3 qa3 qb0 qb0 qb1 qb1 qb2 qb2 qb3 qb3 qb4 26 28 27 25 24 23 22 21 20 19 5678 91011 1 2 3 4 18 16 17 15 14 13 12 v cco v cco v cco pinout: 28-lead plcc (top view)
az100lve210 march 2002 * rev - 3 www.azmicrotek.com 3 100k lvpecl dc characteristics (v ee = gnd, v cc = v cco = +3.3v) -40 c 0 c 25 c 85 c symbol characteristic min t yp max min t yp max min t yp max min t yp max unit v oh output high voltage 1,2 2215 2295 2420 2275 2345 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage 1,2 1470 1605 1745 1490 1595 1680 1490 1595 1680 1490 1595 1680 mv v ih input high voltage 1 2135 2420 2135 2420 2135 2420 2135 2420 mv v il input low voltage 1 1490 1825 1490 1825 1490 1825 1490 1825 mv v bb reference voltage 1 1920 2040 1920 2040 1920 2040 1920 2040 mv i ih input high current 150 150 150 150 a i il input low current 0.5 0.5 0.5 0.5 a i ee power supply current 55 60 55 60 55 60 65 70 ma 1. for supply voltages other that 3.3v, use the ecl table values and add supply voltage value. 2. each output is terminated through a 50 ? resistor to v cc ? 2v. 100k pecl dc characteristics (v ee = gnd, v cc = v cco = +5.0v) -40 c 0 c 25 c 85 c symbol characteristic min t yp max min t yp max min t yp max min t yp max unit v oh output high voltage 1,2 3915 3995 4120 3975 4045 4120 3975 4045 4120 3975 4045 4120 mv v ol output low voltage 1,2 3170 3305 3445 3190 3295 3380 3190 3295 3380 3190 3295 3380 mv v ih input high voltage 1 3835 4120 3835 4120 3835 4120 3835 4120 mv v il input low voltage 1 3190 3525 3190 3525 3190 3525 3190 3525 mv v bb reference voltage 1 3620 3740 3620 3740 3620 3740 3620 3740 mv i ih input high current 150 150 150 150 a i il input low current 0.5 0.5 0.5 0.5 a i ee power supply current 55 60 55 60 55 60 65 70 ma 1. for supply voltages other that 5.0v, use the ecl table values and add supply voltage value. 2. each output is terminated through a 50 ? resistor to v cc ? 2v. ac characteristics (v ee = -3.0v to -5.5v, v cc = v cco = gnd or v ee = gnd, v cc = v cco = +3.0 to +5.5v) -40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit t plh / t phl propagation delay to output in (diff) 1 in (se) 2 475 400 675 700 475 400 675 700 475 400 675 700 475 400 675 700 ps t skew within-device skew part-to-part skew (diff) 3 75 250 75 250 50 200 50 200 ps v pp (ac) minimum input swing 4 250 250 250 250 mv v cmr common mode range 5 v ee + 1.8 v cc - 0.4 v ee + 1.8 v cc - 0.4 v ee + 1.8 v cc - 0.4 v ee + 1.8 v cc - 0.4 v t r / t f rise/fall time 20 ? 80% 200 600 200 600 275 600 275 600 ps 1. the differential propagation delay is de fined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 2. the single-ended propagation delay is de fined as the delay from the 50% point of the input signal to th e 50% point of the o utput signal. 3. the within-device skew is defined as the worst-case difference between any two si milar delay paths within a single device. 4. v pp is the minimum peak-to-peak differential input sw ing for which ac parameters are guaranteed. the v pp (min) is ac limited for the lve210, because differential input as low as 50 mv will still produce full ecl levels at the output. 5. v cmr is defined as the range within which the v ih level may vary, with the device still meetin g the propagation delay specification. the v il level must be such that the peak-to- peak voltage is less than 1.0v and greater than or equal to v pp (min).
az100lve210 march 2002 * rev - 3 www.azmicrotek.com 4 millimeters inches dim min max min max a 12.32 12.57 0.485 0.495 b 12.32 12.57 0.485 0.495 c 4.20 4.57 0.165 0.180 e 2.29 2.79 0.090 0.110 f 0.33 0.48 0.013 0.019 g 1.27 bsc 0.050 bsc h 0.66 0.81 0.026 0.032 j 0.51 0.020 k 0.64 0.025 r 11.43 11.58 0.450 0.456 u 11.43 11.58 0.450 0.456 v 1.07 1.21 0.042 0.048 w 1.07 1.21 0.042 0.048 x 1.07 1.42 0.042 0.056 t 0.50 0.020 z 2 o 10 o 2 o 10 o g1 10.42 10.92 0.410 0.430 k1 1.02 0.040 n otes: 1. datums ?l-, -m-, and ?n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum ?t-, seating plane. 3. dimensions r and u do not include mold flash. alowable mold flash is 0.010mm (0.250in.) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the packge bottom by up to 0.012mm (0.300in.). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be smaller than 0.025mm (0.635in.). package diagram plcc 28
az100lve210 march 2002 * rev - 3 www.azmicrotek.com 5 arizona microtek, inc. reserves the right to change circuitry a nd specifications at any time without prior notice. arizona mic rotek, inc. makes no warranty, representation or guarant ee regarding the suitability of its products for any particular purpose, nor does a rizona microtek, inc. assume any liability arising out of the applica tion or use of any product or ci rcuit and specifically disclaims any and all liability, including without limitation special, consequential or inci dental damages. arizona microtek, inc. does not convey a ny license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as component s in systems intended to support or sustain life, or for any other application in which the fa ilure of the arizona microtek, inc. product could create a situation where personal injury or death may occur. should bu yer purchase or use arizona microtek, inc. products for any such unintended or unauthorized application, buyer shall indemnify a nd hold arizona microtek, inc. a nd its officers, employees, subs idiaries, affiliates, and distri butors harmless against all claims, costs, damages, and expenses, and reasonable a ttorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim al leges tha t arizona microtek, inc. was negligent regarding the design or manufacture of the part.
|
